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zewei / zdma

Data transport between PL and PS on Xilinx ZYNQ -- MSc Thesis at TUC

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ZDMA

Middleware for data transport on Xilinx ZYNQ, MSc Thesis at TUC

The project comprises the following parts:

  • A Vivado hardware design for Zedboard
  • Some HLS image processing cores
  • A Linux 4.x+ kernel driver
  • A user-space library (libzdma)
  • A sample application

Documentation is not here yet.

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Data transport between PL and PS on Xilinx ZYNQ -- MSc Thesis at TUC

License:GNU General Public License v3.0

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Language:Tcl 93.2%Language:C 3.0%Language:Verilog 2.1%Language:C++ 0.8%Language:Shell 0.4%Language:CartoCSS 0.3%Language:BitBake 0.1%Language:Makefile 0.1%Language:Pascal 0.0%Language:GDB 0.0%