xfguo

json-editor

JSON Schema Based Editor

FPGA

帮助大家进行FPGA的入门，分享FPGA相关的优秀文章，优秀项目

verilator

Verilator open-source SystemVerilog simulator and lint system

verilog-ethernet

Verilog Ethernet components for FPGA implementation

corundum

Open source FPGA-based NIC and platform for in-network compute

verilog-axi

Verilog AXI components for FPGA implementation

verilog-pcie

Verilog PCI express components

verilog-axis

Verilog AXI stream components for FPGA implementation

openpiton

The OpenPiton Platform

gtkwave

GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

riscv-aosp

Patches & Script for AOSP to run on Xuantie RISC-V CPU

scastie

An interactive playground for Scala

redir

A TCP port redirector for UNIX

pyuvm

The UVM written in Python

docker-asciidoctor

:ship: A Docker image for using the Asciidoctor toolchain to process AsciiDoc content

circe-yaml

YAML parser for circe using SnakeYAML

openil_linuxptp

PTP IEEE 1588 stack for Linux

Fault

A complete open-source design-for-testing (DFT) Solution

hyperram

Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC

timespec

Functions for working with timespec structures

sc_ethernet

10/100 MII Ethernet MAC for XMOS microcontrollers

sfp-i2c

Read the data of an SFP(+)-module and print it pretty

trime

uvm

Universal Verification Methodology (UVM) base libraries, with edits for Verilator

Single-Cycle-Processor

Single-Cycle RISC-V Processor in systemverylog

hdl-secded-producer

MATLAB/Octave generator of Hamming ECC coding. Output format is Verilog HDL.

HyperRam

simple hyperram controller

BCM53334

交换机

purplebooth-co-uk-v2

Updated version of PurpleBooth.co.uk

Toy-Asynchronous-FIFO-Generator