Giters
olofk
/
edalize
An abstraction library for interfacing EDA tools
Geek Repo:
Geek Repo
Github PK Tool:
Github PK Tool
Stargazers:
609
Watchers:
33
Issues:
157
Forks:
185
olofk/edalize Issues
Symbiflow tool doesn't pass Yosys parameters when using VPR as PnR
Updated
2 months ago
Comments count
1
Edatool.tool_options.get() returns string "None" rather than NoneType
Updated
2 months ago
edalize/flows/edaflow.py # Yeah, I know. It's just a temporary hack
Updated
2 months ago
Comments count
1
Error using f4pga flow for Xilinx
Updated
2 months ago
Passing Verilog string parameters with quotes
Updated
3 months ago
Jinja2 issue witth edarool loader
Updated
3 months ago
Comments count
4
Not possible to fully suppress stdout in edatool API?
Updated
4 months ago
How to read an EDIF netlist into Vivado that isn't the toplevel?
Updated
4 months ago
Incorrect toplevel name used when loading EDIF netlist in Vivado
Updated
4 months ago
Yosys: `configure_main` should check for "file_type" in fileset, or provide a default
Updated
4 months ago
Vivado flow not re-run when Verilog parameter is changed
Updated
4 months ago
Comments count
3
QSys Pro 23 files are not processed correctly by the filter
Closed
5 months ago
Comments count
4
Add update_compile_order to vivado workflow
Closed
6 months ago
Comments count
1
`make_libraries_directories` on Windows fails due to `mkdir -p`
Updated
6 months ago
Comments count
3
Vars do not survive Edaflow
Updated
6 months ago
GHDL Support for cocotb simulation flow
Updated
6 months ago
Comments count
2
Support external tools and flows
Closed
a year ago
Comments count
5
Testsuite fails intermittently
Updated
8 months ago
Comments count
6
Simulating Vivado IPs (xci, bd)
Updated
8 months ago
Comments count
4
explicit dependencies for vunit
Closed
8 months ago
ImportError: cannot import name 'get_edatool' from 'edalize' (unknown location)
Closed
a year ago
Comments count
4
Efinix FPGA support
Closed
10 months ago
Comments count
8
Support a Vivado IP-packaging flow
Updated
a year ago
Comments count
2
Modelsim missing in tools
Updated
a year ago
filelist.py uses python 3.8 syntax
Closed
a year ago
Comments count
5
How best to fix filelist backend
Closed
a year ago
Comments count
3
Xcelium: file list
Updated
a year ago
Comments count
1
Why is the user guide html that I generated empty.
Closed
a year ago
Comments count
3
vivado xsim support for xci or xilinx ip
Updated
a year ago
Comments count
5
Skipping bitstream generation in vivado
Updated
a year ago
Comments count
8
support for include file in yosys
Closed
a year ago
Comments count
2
gnu make on windows 10
Updated
a year ago
Comments count
1
Disabling yosys's synthesis
Updated
a year ago
Comments count
1
F4PGA/Symbiflow Backend
Updated
a year ago
Comments count
12
yosys: wrong target name in Makefile, if output_name tool option is used
Closed
2 years ago
Support for Questasim
Closed
2 years ago
Comments count
1
quartus qsys path seperator on windows 10
Updated
2 years ago
Vivado block design support is broken
Updated
2 years ago
PNR key-value pair gets lost when running vivado
Updated
2 years ago
Comments count
1
usage of packages and tool classes
Updated
2 years ago
Comments count
1
EDAM file: toplevel list of string
Updated
2 years ago
Comments count
1
Ip cores provide to bd file in Vivado did not add to project and updated.
Updated
2 years ago
flow options need to be applied before tool options
Closed
2 years ago
Comments count
1
Yosys, arch=xilinx fails because of syntax error in write_blif command
Closed
2 years ago
Comments count
1
Vivado method missing for programming FPGA (with fusesoc)
Closed
2 years ago
Comments count
6
Improve SymbiFlow backend
Updated
2 years ago
Comments count
7
vopt_options missing in modelsim.py
Updated
2 years ago
Comments count
4
Radiant file types need to include systemVerilogSource
Updated
2 years ago
Use ninja files by default in the Flow API
Updated
3 years ago
Comments count
1
ModelSim makefile is problematic on Windows
Updated
3 years ago
Previous
Next