xfguo

riscv-openwrt

Porting OpenWrt to RISC-V - please check https://github.com/xfguo/riscv-openwrt-port for full instructions.

tbgen

Generate testbench for your verilog module.

riscv-openwrt-port

RISC-V OpenWrt Port

librefpga

A libre implementation of FPGA. Written by chisel.

adv_debug_sys

Advanced Debug System by Nathan Yawn clone from OpenCores.org

rocket-chip

Rocket Chip Generator

rt-thread

RT-Thread is an open source real-time operating system for embedded devices from China.

chisel-template-w-rocket-chip

fpga-zynq

Support for Rocket Chip on Zynq FPGAs

freedom

Source files for SiFive's Freedom platforms

home

China RISC-V User Group Website

riscv-cores-list

RISC-V Cores, SoC platforms and SoCs

riscv-gnu-toolchain

GNU toolchain for RISC-V, including GCC 5.3.0

riscv-linux

RISC-V Linux Port

riscv-openocd

Fork of OpenOCD that has RISC-V support

riscv-pk

RISC-V Proxy Kernel

sifive-blocks

Common RTL blocks used in SiFive's projects

Toy-Parallel-Mux-Generator

cerbero

Cerbero build system used to build the official upstream GStreamer 1.0 SDK binaries

distro

Torch installation in a self-contained folder

freedom-e-sdk

Open Source Software for Developing on the Freedom E Platform

modernist

Modernist is a Jekyll theme for GitHub Pages

netsniff-ng

A Swiss army knife for your daily Linux network plumbing.

risc-v-day-shanghai-2018-souvenir

riscv-card

An unofficial reference card for RISC-V, the free and libre ISA from UC Berkeley.

riscv-openwrt-files

This repo restore some files for riscv-openwrt porting.

scratchip-binary

trepl

A pure Lua-based, lightweight REPL for Torch.

vpn

暂无

zscale

Z-scale Microarchitectural Implementation of RV32 ISA