xfguo

openil_linuxptp

PTP IEEE 1588 stack for Linux

purplebooth-co-uk-v2

Updated version of PurpleBooth.co.uk

corundum

Open source FPGA-based NIC and platform for in-network compute

verilog-ethernet

Verilog Ethernet components for FPGA implementation

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-axi

Verilog AXI components for FPGA implementation

verilog-pcie

Verilog PCI express components

timespec

Functions for working with timespec structures

verilator

Verilator open-source SystemVerilog simulator and lint system

sc_ethernet

10/100 MII Ethernet MAC for XMOS microcontrollers

riscv-aosp

Patches & Script for AOSP to run on Xuantie RISC-V CPU

openpiton

The OpenPiton Platform

Single-Cycle-Processor

Single-Cycle RISC-V Processor in systemverylog

sfp-i2c

Read the data of an SFP(+)-module and print it pretty

docker-asciidoctor

:ship: A Docker image for using the Asciidoctor toolchain to process AsciiDoc content

BCM53334

交换机

HyperRam

simple hyperram controller

hyperram

Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC

circe-yaml

YAML parser for circe using SnakeYAML

Toy-Asynchronous-FIFO-Generator

scastie

An interactive playground for Scala

Toy-Parallel-Mux-Generator

Freedom_on_Nexys_A7

dpdk-switch

A l2 learning switch based on DPDK.

dat.gui

Lightweight controller library for JavaScript.

vcd_parsealyze

A Value Change Dump (VCD) file parser and analyzer

v8

Port of Google v8 engine to RISC-V.

v8-riscv

PLCT实验室 V8 for RISC-V 的主仓库。2020年完成部署。

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

uvm-python

UVM 1.2 port to Python