luojw-dwr / Toy-Asynchronous-FIFO-Generator

Toy Asynchronous FIFO Generator

(This repository originated as a submission to CNRV Challenge CH002.)

This project offers an chisel3 reinterpretation of the Verilog code from the well-known article Simulation and Synthesis Techniques for Asynchronous FIFO Design.

Generation

Before generating your desired asynchronous FIFO, modify src/main/scala/afifo/main.scala to achieve a correct data type and depth (and number of stages of pointer flopping synchronizer whose default is 2 in both directions). Assuming that you have changed to the project root directory, run the following in your terminal:

$ make build

The generated annotations, firrtl files and verilog files should lie in build/.

Simulation

The simulation files are modified from those provided by the repository dpretet/async_fifo. Please make sure to have GTKWave, Icarus Verilog and SVUT installed. Assuming that you have changed to the project root directory.

CLI Test

If you only want to read the report, run the following in your terminal:

$ cd src/test/svut
$ make test

The simulation report should show in the terminal.

GUI Test

If you want to have a glance at the waves, run the following in your terminal:

$ cd src/test/svut
$ make gui

GTKWave will then be launched while the simulation report should show in the terminal. Some simulation-related files will be generated at the same time, to delete which:

$ cd src/test/svut
$ make clean

Source Files

• Main Components:
  • AsyncFIFO.scala: The top-level module for the asynchronous FIFO.
  • WCtrl.scala: The controller of the writing side. Pointer CDC is handled internally.
  • RCtrl.scala: The controller of the reading side. Pointer CDC is handled internally.
  • S2P.scala: A simple dual port memory model where neither the address nor the data is registered. If any complicated bundles are to be stored, each bundle will be stored as a whole UInt internally (rather than separate fields) while the module takes care of the type conversions.
• Miscellaneous logics:
  • gray.scala: Binary->Gray conversion logic and gray-encoded pointer comparison logics.
• Interface bundles:
  • CtrlPtrIO.scala: Pointer exchange interface for WCtrl and RCtrl.
  • MemReadPortCtrlIO: Read clock and read address.
  • MemWritePortCtrlIO: Write clock, write enable and write address.
  • MemReadPortIO: MemReadPortCtrlIO and read data.
  • MemWritePortIO: MemWritePortCtrlIO and written data.

Design Internals

The module is separated into three components (corresponding to the clock domains coincidentally):

The pointer CDC are handled with gray codes and the pointers are synchronized inside both controllers.