Course taken by Dr Chandan Karfa of Dept. of CSE, IIT Guwahati.
High-level Synthesis (HLS) is the process of generating effecient hardware at register transfer level (RTL) from the input C-code (high-level code). HLS is an active domain of research in recent times in the domain of electronic Design Automation (EDA) of VLSI. This course will help the students to understand
the overall C to RTL synthesis flow, how a C-code will be converted to its equivalent hardware, how to write C-code for efficient hardware generation, how the common software compiler optimizations can help to improve the circuit performance. Hardware Acceleration of Machine Learning Algorithm Secure Hardware generation using HLS Equivalence checking between C and RTL. The overall EDA tool flow.
This course will help the students to take up research in the domain of HLS. Also, this course will help the students to become proficient for EDA industries.
Pre-requisites: (1) Basic knowledge of digital circuits (2) Basic knowledge of Data structures and algorithms.