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SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.
Autotuning High-Level Synthesis for FPGAs, published @ ReConFig '17
This repository contains CHStone benchmark codes which have been annotated and tuned by Orio tool to test the speed up of execution.
Auto-Tuning chain to optimize software execution and compilation time upon heterogeneous systems
Automated adaptive clock management tool for LegUp HLS-generated circuits on FPGA.