The goal for this project was to create a custom instruction and hardware to support the custom instruction, with the effect of hardware accelerating a specific computation, and returning the result to the NIOs II soft-core processor. The custom logic was designed in SystemVerilog and instantiated on the FPGA fabric alongside the NIOS II core and other hardware such as timers and interruprt handlers. The project was completed in Quartus Prime 21.1 Lite and tested with the Altera DE1 board.