sudhamshu091 / Single-Cycle-Risc-Pipelined-Processor-Verilog

Single Cycle MIPS Pipelined Processor using Verilog

Single-Cycle-Risc-Pipelined-Processor-Verilog

Trying to implement a single cycle MIPS computer in Verilog that supports MIPS assembly instructions including:

• Memory-reference instructions load word lw and store word sw
• Arithmetic-logical instructions add, addi, sub, and, andi, or, and slt
• Jumping instructions branch-equal beq and jump j

Below image is the Risc processor I am trying to impleent, But end product may not be exactly the same.
Image Source: Click Here

Waveform

RTL