Tim 'mithro' Ansell (mithro)

mithro

Geek Repo

Company:@timvideos

Location:Sunnyvale, US

Home Page:https://blog.mithis.net/

Twitter:@mithro

Github PK Tool:Github PK Tool


Organizations
alainmarcel
events-everywhere
freecores
fupy
hdl
im-tomu
sydney-linux-user-group
sydney-linux-user-group-dependencies
SymbiFlow
thousandparsec
timvideos

Tim 'mithro' Ansell's repositories

kicad-pmod

KiCad Library to make it easy to create both host boards and expansion boards and which are compatible with the Digilent "PMOD" specification.

asap7_snps

Supplemental technology files for ASAP7 PDK with Synopsys design flow

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OpenRAM

An open-source static random access memory (SRAM) compiler.

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SOFA

SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA

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Fault-SPM

SPM with DFT structure automatically injected by Fault

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ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

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pp4fpgas

Parallel Programming for FPGAs -- An open-source high-level synthesis book

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python-fpga-interchange

Python interface to FPGA interchange format

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requirements.py

Package for querying Python `requirements.txt` files which uses `pip`'s own parser.

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sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

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actions

GitHub Actions to be reused in CI workflows

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bsg_fakeram

fakeram generator for use by researchers who do not have access to commercial ram generators

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checkout

Action for checking out a repo

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continuous-integration

Bazel's Continuous Integration Setup

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docs

The open-source repo for docs.github.com

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fulcio

SigStore WebPKI

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litex-conda-eda

Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.

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NetCracker

NetCracker is an FPGA architecture analysis tool for facilitating the investigation of connectivity patterns within as well as in between switchboxes

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netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists

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osvb

Open Source Verification Bundle for VHDL and System Verilog

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python-sdf-timing

Python library for working Standard Delay Format (SDF) Timing Annotation files.

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python-symbiflow-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

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rapidyaml

Rapid YAML - a library to parse and emit YAML, and do it fast.

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sphinx_symbiflow_theme-old

Material Design Html Theme for Sphinx.

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symbiflow-rr-graph

Collection of Routing Resources Graph (RR Graph) libraries for VPR

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symbiflow-tools-data-manager

Python based package manager to get packages and artifacts of symbiflow projects

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