FreeCores

FreeCores's repositories

ethmac

Ethernet MAC 10/100 Mbps

Language:Verilog75 7 2

jpegencode

JPEG Encoder Verilog

Language:Verilog66 7 1

i2c

I2C controller core

Language:Verilog30 4 2

turbo8051

turbo 8051

Language:Verilog30 50

embedded_risc

Embedded 32-bit RISC uProcessor with SDRAM Controller

Language:Verilog23 30

freecores.github.io

Freecores website

Language:CSS19 10 1

mips_16

Educational 16-bit MIPS Processor

Language:Verilog17 30

zx_ula

ULA chip for ZX Spectrum

Language:Verilog17 40

ps2

PS2 interface

Language:Verilog16 30

zet86

Zet - The x86 (IA-32) open implementation

Language:CGPL-3.016 40

mmu180

MMU for Z80 and eZ80

Language:Verilog15 50

zpu

ZPU - the worlds smallest 32 bit CPU with GCC toolchain

Language:VHDL15 30

mmuart

Simple RS232 UART

Language:Verilog13 40

tiny_aes

AES

Language:VerilogApache-2.013 30

wb_builder

WISHBONE Builder

Language:Perl13 60

avr_core

AVR Core

12 40

sc2v

SystemC to Verilog Synthesizable Subset Translator

Language:CGPL-2.09 20

aes_core

AES (Rijndael) IP Core

Language:Verilog6 20

minirisc

Mini-Risc core

Language:Verilog6 50

des

DES/Triple DES IP Cores

Language:Verilog5 20

altor32

AltOr32 - Alternative Lightweight OpenRisc CPU

Language:VerilogLGPL-3.04 60

ao486

Language:C++4 2 1

systemcmd5

SystemC/Verilog MD5

Language:C++4 40

zbt_sram_controller

ZBT SRAM Controller

Language:VHDLNOASSERTION4 30

myforthprocessor

FORTH processor with Java compiler

Language:Java3 20

xtea

XTEA Crypto Core

Language:VerilogLGPL-2.13 20

test_project

No description

Language:C2 20

opb_wb_wrapper

WB/OPB & OPB/WB Interface Wrapper

Language:Verilog1 30

lem1_9min

LEM1_9

Language:VHDL020

zorro_to_wishbone_bridge

Zorro bus to Wishbone bridge

020