SureLog - UHDM (alainmarcel)

SureLog - UHDM

alainmarcel

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SureLog - UHDM's repositories

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

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UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

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Help_Wanted

Ideas that need engineering-power from the community for UHDM/Surelog/Related topics

antlr4

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

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sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

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tsc

CHIPS Alliance Technical Steering Committee

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yosys

Yosys Open SYnthesis Suite

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