SureLog - UHDM

Surelog

SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Help_Wanted

Ideas that need engineering-power from the community for UHDM/Surelog/Related topics

yosys-uhdm-plugin-integration

antlr4

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

EasyCLA-code_only

simview

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

tsc

CHIPS Alliance Technical Steering Committee

UHDM-integration-tests

verilator

yosys

Yosys Open SYnthesis Suite