Scoreboard with Countdown Timer; FPGA deisgned in Verilog using Vivado:
Important
Demo Video Link
Meet the team:
This project was completed in EGCP 446 Fall 2022 by Duy, Jeremy and Spencer. Spencer contributed the module used to keep team scores, I contributed by creating the countdown timer. Lastly, Duy setup the 7 segment!
Initial setup:
Install Xilinx Vivado
Download zip folder:
Open vivado and import project to IDE
Connect FPGA board:
Make sure to select correct FPGA board, Nexy's A7
Create Bitstream:
Once created you can then load program unto board and test software running.
Screen shot of FPGA board:
Warning
Copyright ©2023 Duy, Jeremy and Spencer, MIT License