Henner Zeller (hzeller)

hzeller

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Location:San Francisco

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Henner Zeller's repositories

rpi-rgb-led-matrix

Controlling up to three chains of 64x64, 32x32, 16x32 or similar RGB LED displays using Raspberry Pi GPIO

Language:C++License:GPL-2.0Stargazers:3523Issues:178Issues:1471

timg

A terminal image and video viewer.

Language:C++License:GPL-2.0Stargazers:1784Issues:27Issues:85

gmrender-resurrect

Resource efficient UPnP/DLNA renderer, optimal for Raspberry Pi, CuBox or a general MediaServer. Fork of GMediaRenderer to add some features to make it usable.

Language:CLicense:GPL-2.0Stargazers:827Issues:61Issues:230

txtempus

A DCF77, WWVB, JJY and MSF clock LF-band signal transmitter using the Raspberry Pi

Language:C++License:GPL-3.0Stargazers:403Issues:41Issues:22

beagleg

G-code interpreter and stepmotor controller for crazy fast coordinated moves of up to 8 steppers. Uses the Programmable Realtime Unit (PRU) of the Beaglebone.

Language:C++License:GPL-3.0Stargazers:120Issues:30Issues:28

augenmass

Measure relative sizes on background image.

stuff-org

Organize electronic components. Or other stuff.

folve

Folve - seamlessly FIR convolving audio file fuse filesystem with gapless support.

Language:C++License:GPL-3.0Stargazers:31Issues:9Issues:2

trs80-100-schematic

A transcript of the TRS80 Model 100 schematic

digi-spherometer

A digital spherometer, reading data from digital dial indicator and converting it to radius, displaying on OLED display.

Language:C++License:GPL-3.0Stargazers:14Issues:3Issues:0

sound-cam

Simulation of using Microphones to pick up sound locations.

Language:C++Stargazers:5Issues:4Issues:0

simple-fasm

A simple parser for the FPGA Assembly format

Language:C++License:Apache-2.0Stargazers:3Issues:4Issues:0

ziplain

A plain, no-frills ZIP file writer.

Language:C++License:Apache-2.0Stargazers:3Issues:2Issues:0

Surelog

System Verilog 2017 Pre-processor, Parser

Language:C++License:Apache-2.0Stargazers:2Issues:2Issues:0

UHDM

Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, Visitor and Listener. Used as a compiled interchange format in between SystemVerilog tools. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX

Language:C++License:Apache-2.0Stargazers:2Issues:1Issues:0

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Language:C++License:NOASSERTIONStargazers:2Issues:2Issues:0

gaggia-pid

PID controller, useful for e.g. coffee machines.

Language:C++Stargazers:1Issues:2Issues:0

olive

Professional open-source NLE video editor

Language:C++License:GPL-3.0Stargazers:1Issues:2Issues:0

opentitan

OpenTitan: Open source silicon root of trust

Language:SystemVerilogLicense:Apache-2.0Stargazers:1Issues:2Issues:0

sv-tests

Test suite designed to check compliance with the SystemVerilog standard.

Language:SystemVerilogLicense:ISCStargazers:1Issues:2Issues:0

abc

ABC: System for Sequential Logic Synthesis and Formal Verification

Language:CLicense:NOASSERTIONStargazers:0Issues:1Issues:0

antlr4

ANTLR (ANother Tool for Language Recognition) is a powerful parser generator for reading, processing, executing, or translating structured text or binary files.

Language:JavaLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0

nixpkgs

Nix Packages collection

Language:NixLicense:MITStargazers:0Issues:1Issues:0

OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow

Language:VerilogLicense:BSD-3-ClauseStargazers:0Issues:1Issues:0

qoi

The “Quite OK Image Format” for fast, lossless image compression

Language:CStargazers:0Issues:1Issues:0

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

Language:C++License:NOASSERTIONStargazers:0Issues:1Issues:0
Language:C++License:LGPL-3.0Stargazers:0Issues:1Issues:0

yosys

Yosys Open SYnthesis Suite

Language:C++License:ISCStargazers:0Issues:3Issues:0

yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:1Issues:0

yosys-systemverilog

SystemVerilog support for Yosys

Language:VerilogLicense:Apache-2.0Stargazers:0Issues:1Issues:0