fardinabbasi / RISC-V_Processor_Pipelined

Digital Systems 2 Course [ECE 778] - CA4 - Spring 2023 - University of Tehran - Dr. Safari

Pipelined RISC-V Processor

Design and implementation of RISC-V processor with a pipelined datapath, controller, and hazard unit.

Commands

R_Type:  add, sub, and, or, slt

I_Type:  lw, addi, xori, ori, slti, jalr

S_Type:  sw

J_Type:  jal

B_Type:  beq, bne, blt, bge

U_Type:  lui

Datapath

Controller

Immediate Extension Unit Controller

ALU Opcode Controller

ALU Controller

Hazard Unit

Test Code

The following assembly code can be converted to machine code using RISC-V Online Assembler.

addi X7,X0,16;
addi X8,X0,30;
sub X9,X8,X7;
and X10,X8,X7;
or X11,X8,X7;
slt X12,X8,X7;
xori X13,X7,13;
ori X14,X7,13;
slti X15,X7,13;
sw X8,400(x7);
lui X17,60;
jalr X16,X7,10;