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A single cycle MIPS RISC-V CPU Core using Verilog

RISC-V-CPU-Core

A single cycle MIPS RISC-V CPU Core using Verilog

Abstract

RISC-V is an open source Instruction Set Architecture (ISA). In this project I have implemented a 32-bit, RISC-V ISA based processor in verilog and verified execution of instructions in RISC-V ISA. The sub-modules that are used and their interaction with each other are shown in the following picture.

Final datapath in Xilinx Vivado

Datapath without bundled nets

Output waveforms in Xilinx Vivado

Synthesized design of the processor in Xilinx Vivado