Compile SystemRDL into a SystemVerilog control/status register (CSR) block.
For the command line tool, see the PeakRDL project.
See the PeakRDL-regblock Documentation for more details
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Compile SystemRDL into a SystemVerilog control/status register (CSR) block.
For the command line tool, see the PeakRDL project.
See the PeakRDL-regblock Documentation for more details
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
http://peakrdl-regblock.readthedocs.io
GNU General Public License v3.0