Giters
RoaLogic
/
RV12
RISC-V CPU Core
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Stargazers:
275
Watchers:
20
Issues:
15
Forks:
50
RoaLogic/RV12 Issues
minstret not counting BEQ
Closed
a month ago
Linux compatibility
Updated
2 years ago
Comments count
2
ICACHE_WAYS = 1 and/or DCACHE_WAYS = 1 fails Xilinx Synthesis
Closed
2 years ago
Comments count
3
Debug Control
Updated
2 years ago
Comments count
1
Synth Error: Illegal biu_size_t
Updated
2 years ago
Comments count
2
casex processing
Closed
2 years ago
Comments count
1
Design elaboration failed in Xilinx Vivado
Closed
2 years ago
Comments count
1
Potential bug with consecutive LOAD instructions
Closed
2 years ago
Comments count
7
Error: rl_ram_1r1w not found in branch prediction unit
Closed
4 years ago
can't run simulation with vcs
Updated
5 years ago
can't find Wishbone stuff in the github RoaLogic/RV12 repo
Closed
7 years ago
Comments count
2
can't run simulation with iverilog
Closed
7 years ago
Comments count
1
Documents Update
Closed
7 years ago
Comments count
5
about the core simulation
Closed
7 years ago
Comments count
1
Reading MCYCLE causes trap
Closed
6 years ago
Comments count
1