RoaLogic / RV12

RISC-V CPU Core

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casex processing

eshellko opened this issue · comments

I've found that you are using 'casex' for decoders implementation with HEX digits in it.
It could be potential problem. Actually, I've checked only 1 file (riscv_du.sv) and here are my thoughts.
If 'du_exceptions' can have more than 1 bits asserted at time, 'dbg.cause' casex would probably works not as expected.

  //DBG CAUSE
  always @(posedge clk,negedge rstn)
    ...
    else if (|du_exceptions[15:0]) //traps
    begin
        casex (du_exceptions[15:0])
          16'h???1 : dbg.cause <=  0;
          16'h???2 : dbg.cause <=  1;
          16'h???4 : dbg.cause <=  2;
		  ...
          default  : dbg.cause <=  0;
        endcase
    end

My expectation that for 'du_exceptions' = 0x6 result should be 1. But at the moment it will be 0 (default case item).

du_exceptions   dbg.cause (my expectation)
 0x0001             0
 0x0002             1
 0x0003             0
 0x0006             1  -- but here 'default' case item selected and 'dbg.cause' = 0

Probably better way to decode such logic is to use BIN digits like this:
16'b????????????_??10 : cause <= 1;

Again, this could be a problem, if my expectations are right, otherwise you can freely ignore this message.
I've attached simple testbench that illustrates the issue.
tb.zip

Fixed in dev branch