ICACHE_WAYS = 1 and/or DCACHE_WAYS = 1 fails Xilinx Synthesis

[Dustin Richmond]

Error message:

ERROR: [Synth 8-523] part-select [-1:0] does not match declaration [riscv_icache_core.sv:381]

Reference is to this line:

  assign fill_way_select_rnd = 1 << way_random[LRU_BITS-1:0];

Where LRU_BITS = $clog2(WAYS). I believe this fix is:

generate
  if(LRU_BITS == 0)
    assign fill_way_select_rnd = 1;
  else
    assign fill_way_select_rnd = 1 << way_random[LRU_BITS-1:0];
endgenerate

Happy to generate a PR if this seems correct

[rherveille]

Hi Dustin,

Thanks for reporting this. This is a currently known/confirmed limitation. WAYS=1 generates a direct-mapped cache, but LRU_BITS=0 breaks the code and I believe on more than just fill_way_select_rnd. Can you please confirm the Xilinx tool does not generate other errors with your fix?

Thanks,
Richard

[Dustin Richmond]

Hi Richard

I can confirm that this fixes all synthesis issues.

I don't know if this is a related issue, but my notes say: "dcache returns same data for ADDR + 0 and ADDR + 4 when LINE_SIZE > XLEN" -- I don't know how accurate that is

I found it it a week ago and haven't been able to examine it since because of moving/travel/holidays (and unfortunately, it's been paged out of my brain).

I'll have more time to examine this after the new year

Thanks!
Dustin

[rherveille]

Hi Dustin,

I just released a new version of the core. This adds a new 'mem' stage which improves memory access timing.
I also fixed the WAYS issue you reported and another I$ bug that showed up.

Cheers,
Richard