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RoaLogic / RV12

RISC-V CPU Core

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can't find Wishbone stuff in the github RoaLogic/RV12 repo

frantony opened this issue · comments

commented

The top RV12 README.md file states that RV12 supports Wishbone interface.

I can't find any traces of Wishbone in RV12 version v1.1-rc1 (408e335).
Also there is no Wishbone mention in the 'External interfaces' section of RV12 documentation (docs/tex/06-external-if.tex).

commented

Hello Antony - Thanks for the feedback. Couple of feedback points for you:

  1. Wishbone: The reference to Wishbone should not have been in the README. We have a verison of RV12 with Wishbone support under development but it is not yet complete and the README reference was an oversight that should have been removed.

  2. Please note that the commit you reference is not the latest release - there were a couple of minor updates after that RC was created. Latest is here

  3. Update coming: I have created a new branch with a correction to the README and also included your VIM swap file fix. You can find that here. We will check for other incorrect file inclusions and then release this version asap.

commented

v1.2 is now released with the noted documentation update and removal of the unnecessary swap file. Wishbone support is a work in progress - we don't have an ETA for completion yet

As a consequence I will close this issue