PyFPGA / hdl2vlog

VHDL / System Verilog to Verilog converter, based on Yosys and the plugins ghdl-yosys-plugin and synlig.

hdl2vlog

WARNING: this is a WIP project in an early stage (Sep, 2023).

VHDL / System Verilog to Verilog converter, based on Yosys, and the plugins ghdl-yosys-plugin and synlig. It relies on Docker and PyFPGA containers.