DesperateExplorer

gym

A toolkit for developing and comparing reinforcement learning algorithms.

faiss

A library for efficient similarity search and clustering of dense vectors.

jax

Composable transformations of Python+NumPy programs: differentiate, vectorize, JIT to GPU/TPU, and more

500lines

500 Lines or Less

bullet3

Bullet Physics SDK: real-time collision detection and multi-physics simulation for VR, games, visual effects, robotics, machine learning etc.

LaTeX-OCR

pix2tex: Using a ViT to convert images of equations into LaTeX code.

mujoco

Multi-Joint dynamics with Contact. A general purpose physics simulator.

awesome-multimodal-ml

Reading list for research topics in multimodal machine learning

ai-deadlines

:alarm_clock: AI conference deadline countdowns

hedgedoc

HedgeDoc - Ideas grow better together

CLRS

📚 Solutions to Introduction to Algorithms Third Edition

PromptPapers

Must-read papers on prompt-based tuning for pre-trained language models.

gpytorch

A highly efficient implementation of Gaussian Processes in PyTorch

learn2learn

A PyTorch Library for Meta-learning Research

Cheetah-Software

MAML-Pytorch

Elegant PyTorch implementation of paper Model-Agnostic Meta-Learning (MAML)

ml-pen-and-paper-exercises

Pen and paper exercises in machine learning

ml-cvnets

CVNets: A library for training computer vision networks

higher

higher is a pytorch library allowing users to obtain higher order gradients over losses spanning training loops rather than individual training steps.

StanfordQuadruped

THU-PPT-Theme

清华主题PPT模板

PrefixTuning

Prefix-Tuning: Optimizing Continuous Prompts for Generation

thuhole_memories

optimaltransport.github.io

Web site of the Computational Optimal Transport book

pssh

Parallel SSH Tools

Graduate_Application

Documents used for grad school application

fedar-f1-rv64im

5-Stage Pipelined RV64IM RISC-V CPU design in Verilog.

THU-Exam-LaTeX-Template

A LaTex Template for THU Examination

fedar-e1-rv32i

5-Stage Pipelined RV32I RISC-V Core design in Verilog-2005. It has 32 GPIO pins and it is FPGA synthesible.

tage

Implementation of TAGE Branch Predictor - currently considered state of the art