Arvind-Srinivasan / Verilog-Projects

A variety of projects using FOSS Verilog tools for the Alchitry CU

Verilog Projects

A variety of projects using a FOSS Verilog toolchain for Lattice iCE40 FPGAs on the Alchitry Cu.

FOSS Software Toolchain

• Verilator
• ICARUS Verilog
• Yosys Open SYnthesis Suite
• nextpnr
• Project IceStorm
• Alchitry Loader

Hardware

Uses relatively low-cost (~$75) parts:

• Alchitry Cu dev board
  • iCE40-HX8K FPGA with 100 MHz clock
  • Schematic
• Alchitry Io expansion board
  • Provides all needed IO connections
  • Schematic

Software

This project was tested to run on macOS Mojave 10.14.6, and may not work on other operating system or macOS versions. The following brew packages are required:

• make
• verilator
• icarus-verilog
• yosys
• ktemkin/oss-fpga/nextpnr-ice40
• ktemkin/oss-fpga/icestorm

Install via the install.sh script

./install.sh

Projects

Binary Counter

Simple project using the 8 Cu LEDs to count up to 2⁸ and display binary values.

Decimal Counter

Simple project using the 24 Io LEDs to count up to 24 and displays values.

Resources

• Verilator (used for linting of Verilog source files)
• ICARUS Verilog (used for simulation of Verilog source files)
• yosys – Yosys Open SYnthesis Suite (synthesis of Verilog source files)
• nextpnr (used for placement and routing after synthesis)
• Project IceStorm (used for timing analysis and bitstream generation)
• Alchitry Loader (fork with macOS support for uploading to the Alchitry Cu)
• Scansion (software used to read VCD files)
• ASIC World (Verilog reference)
• iCEBreaker examples (useful Verilog examples for common tasks)
• Verilog OS X (useful makefile and simulation example)
• Cu-Base-Project (base Alchitry Verilog project)
• Alchitry Labs (Alchitry IDE providing some default files and examples)

License

This project is licensed under the MIT License. See the LICENSE file for more information.