Ang-Andrew's starred repositories

build-your-own-x

Master programming by recreating your favorite technologies from scratch.

awesome-selfhosted

A list of Free Software network services and web applications which can be hosted on your own servers

LeetCode-Go

✅ Solutions to LeetCode by Go, 100% test coverage, runtime beats 100% / LeetCode 题解

budibase

Low code platform for building business apps and workflows in minutes. Supports PostgreSQL, MySQL, MSSQL, MongoDB, Rest API, Docker, K8s, and more 🚀

Language:TypeScriptLicense:NOASSERTIONStargazers:21048Issues:213Issues:4337

awesome-microservices

A curated list of Microservice Architecture related principles and technologies.

leetcode-patterns

A pattern-based approach for learning technical interview questions

Language:JavaScriptLicense:GPL-3.0Stargazers:9620Issues:113Issues:125

resume

Software developer resume in Latex

Language:TeXLicense:MITStargazers:4808Issues:48Issues:32

interviews.ai

It is my belief that you, the postgraduate students and job-seekers for whom the book is primarily meant will benefit from reading it; however, it is my hope that even the most experienced researchers will find it fascinating as well.

mobile-system-design

A simple framework for mobile system design interviews

darkriscv

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

Language:VerilogLicense:BSD-3-ClauseStargazers:1925Issues:86Issues:40

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Language:PythonLicense:BSD-3-ClauseStargazers:1656Issues:106Issues:1783

AI-Chip

A list of ICs and IPs for AI, Machine Learning and Deep Learning.

corundum

Open source FPGA-based NIC and platform for in-network compute

Language:VerilogLicense:NOASSERTIONStargazers:1516Issues:86Issues:152

stm32-usart-uart-dma-rx-tx

STM32 examples for USART using DMA for efficient RX and TX transmission

openc910

OpenXuantie - OpenC910 Core

Language:VerilogLicense:Apache-2.0Stargazers:1071Issues:45Issues:24

axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

Language:SystemVerilogLicense:NOASSERTIONStargazers:960Issues:38Issues:117

OpenLog

Open Source Hardware Datalogger

Language:C++License:NOASSERTIONStargazers:537Issues:98Issues:240

basejump_stl

BaseJump STL: A Standard Template Library for SystemVerilog

Language:SystemVerilogLicense:NOASSERTIONStargazers:458Issues:28Issues:180

LittleBrain-STM32F4-Sensorboard

STM32F4-based PCB interfacing with a variety of sensors.

NiteFury-and-LiteFury

Public repository for Litefury & Nitefury

Language:SystemVerilogStargazers:254Issues:26Issues:54

ztachip

Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.

Language:VHDLLicense:MITStargazers:205Issues:8Issues:9

cocotbext-axi

AXI interface modules for Cocotb

Language:PythonLicense:MITStargazers:188Issues:13Issues:62

Rudi-RV32I

A rudimental RISCV CPU supporting RV32I instructions, in VHDL

Language:VHDLLicense:MITStargazers:111Issues:13Issues:0

alldigitalradio

All Digital Radio Platform written in nmigen targeting FPGAs (for now)

Language:Jupyter NotebookLicense:Apache-2.0Stargazers:78Issues:7Issues:0

polyphony

3D graphics rendering system for FPGA, the project contains hardware rasterizer, software geometry engine, and application middleware.

Language:VerilogLicense:MITStargazers:62Issues:2Issues:1

cocotbext-eth

Ethernet interface modules for Cocotb

Language:PythonLicense:MITStargazers:48Issues:8Issues:3

BrightAI-Blackwire

BrightAI B.V. open sources its Blackwire RTL FPGA smartNIC implementation of WireGuard

License:BSD-3-ClauseStargazers:44Issues:0Issues:0

DSCAM

Directly Synthesized Content-Addressable Memory (DSCAM) is an innovative method to implement very large CAMs on FPGAs. DSCAM offers guaranteed low-latency and high throughput lookups with an affordable resource utilization compared to related works.

Language:PythonLicense:BSD-2-ClauseStargazers:8Issues:0Issues:0