pulp-platform / axi

AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication

pulp-platform/axi Issues

Support for Generating Sparse Connection Crossbar
Updated a month ago
prdata_i declaration in axi_lite_to_apb.sv is incorrect
Updated 2 months ago
axi_xbar_unmuxed: Avoid multi dimensional arrays in more tools
Updated 2 months ago1
is AxiMaxReads useful in axi_dwc ?
Updated 3 months ago
Vivado Synthesis Error - [Synth 8-6038] cannot resolve hierarchical name
Updated 4 months ago1
Documentation error
Updated 5 months ago
Can't find cdc_fifo_gray_dst
Closed 5 months ago2
`axi_to_mem`: Comb path from `b_ready` to `w_ready`
Updated 5 months ago2
Why is `xbar_latency_e` an `enum`?
Closed 7 months ago1
Expose `AxiLookBits` as a parameter in `axi_burst_splitter`
Updated 7 months ago1
Error when IdMapNumEntries =0 with VCS
Updated 8 months ago
"MaxTrans" defined incorrectly in the module documentation
Updated 8 months ago
Compile errors with CDC module
Updated 9 months ago
axi_sim_mem write after read leads to AXI error
Updated 10 months ago1
axi_cdc fpga implementation very inefficient
Updated 10 months ago2
AXI Demux could be extended to send requests with same ID to different slaves
Updated a year ago6
Pipelines between demux and mux would still cause deadlock in an axi_xbar?
Updated a year ago2
AXI_BUS and AXI_BUS_DV package missing?
Closed a year ago2
Logging not supported for Queue item error : AXI
Updated a year ago2
axi_iw_convertor connection
Updated a year ago
axi_dw_downsizer writing data beats with wstrb == 0
Updated a year ago
``axi_to_mem``: Error response signals in B and R response channels
Closed a year ago
tb_axi_lite_xbar is not included in scripts/run_vsim.sh
Updated a year ago
run_vsim.sh: Run simulations in parallel
Updated 2 years ago4
axi_pkg::LenWidth not compatible with vivado IP packager
Closed 2 years ago
axi_to_mem: Starvation issue: AW channel blocks AR channel forever
Updated 2 years ago
axi_dw_downsizer: AXI Slave BRESP changes in value during BVALID’s wait for BREADY
Updated 2 years ago
[Question] AXI Ordering
Updated 2 years ago
Improve AXI cut/multicut.
Updated 2 years ago
Should we add an option to force aligned accesses of given `ax_size` in class `axi_rand_master`?
Closed 2 years ago1
Example of usage for axi_to_axi_lite converter
Updated 2 years ago
axi.core needs dependency for common_verification
Updated 2 years ago
Reporting SystemVerilog issues to EDA vendors
Closed 2 years ago1
Support Xilinx Vivado Simulator
Closed 2 years ago9
`axi_burst_splitter` inverse functionality for Modifiable bit
Closed 2 years ago1
`axi_to_mem_banked` demux hardware overhead
Updated 2 years ago
axi crossbar MaxSlvTrans and MaxMstTrans not working as expected
Updated 2 years ago
`axi_driver` not included in the FuseSoc core file
Updated 2 years ago
Tie mst_w_chan to '0 when mst_w_valid!=0.
Closed 2 years ago1
Monitor modport on AXI_BUS and AXI_LITE interfaces
Closed 2 years ago2
Running testbenches with Verilator or Vivado
Updated 2 years ago3
about the full_o of IDcounter
Updated 2 years ago1
Write ordering problem with axi_sim_mem
Updated 2 years ago1
Replacing axi_node_wrap_with_slices with axi_xbar in Ariane/CVA6
Updated 2 years ago5
How to synthesize with Genus?
Closed 2 years ago3
AXI_BUS instead of AXI_LITE in axi_lite_mux_intf
Closed 3 years ago1
`axi_(lite_)_(de)mux`: Single master/slave edge case ignores spill parameters
Closed 3 years ago1
Compilation error of axi_lite_mux_intf with XSim
Closed 3 years ago1
the error when run axi_intercon_gen.py
Closed 3 years ago1
rand_id_queue_pkg not found
Closed 3 years ago1