Beast code in Giters

Ang-Andrew's repositories

brimstone

Brimstone: Single Cycle MIPs Processor

Language:Verilog1 20

HD44780U-LCD-example-for-zedboard

Language:VHDL1 20

ZedBoard_tutorial

Understanding the Zedboard

Language:VHDL1 20

aes_encryption_vhdl_implementation

An Advanced Encryption Standard (AES) implementation in VHDL

Language:VHDL020

Ang-Andrew.github.io

Personal website

Language:HTML020

avr_hello_world

Simple example of using Docker to compile for AVR microcontrollers

Language:MakefileMIT020

CPU_4001

4001 CPU emulator in C++

Language:C++020

rhodonite

Language:Verilog000

rust_explore

Language:Rust020

Supabase-tutorial

Language:JavaScript020

Custom_arduino_pcb

Custom circular arduino PCB

Language:HTML020

dotfiles

Personal dotfiles

Language:Shell020

ECEN301_labs

Language:C020

ECEN425-Range-Finder

Language:Arduino000

FPGA_projects

Language:C020

fullstack-admin

Language:JavaScript000

HackerRank

Solutions to HackerRank problems

Language:PythonMIT010

MPU6050-Servo-Interface

MPU6050 Servo interface

Language:Arduino020

PCB_Business_card

PCB Business Card

020

Plate-Detector

MATLAB script that gets car plate information

Language:Matlab000

springboot-explore

Language:Java000

TorchApp

Language:Java020

uart_verilog

Language:Verilog020

uart_vhdl

Simple UART engine implementation in VHDL. Target clock frequency of 250 MHz running on the Pynq-Z1

Language:VHDL000

VHDL

Language:VHDL020

Vivado_HLS_training

Vivado HLS training

Language:VHDL020

wishbone_bus_vhdl_implementation

Implementation of wishbone bus in VHDL

Language:VHDL020

yelp_clone

Language:JavaScript000