201934744

201934744

Geek Repo

Github PK Tool:Github PK Tool

201934744's starred repositories

prjxray-experiments-archive-2017

These are experiments which we conducted in 2017 as part of Project X-Ray.

Language:VerilogLicense:ISCStargazers:2Issues:0Issues:0

f4pga-examples

Example designs showing different ways to use F4PGA toolchains.

Language:VerilogLicense:Apache-2.0Stargazers:262Issues:0Issues:0

f4pga

FOSS Flow For FPGA

Language:PythonLicense:Apache-2.0Stargazers:345Issues:0Issues:0

vtr-verilog-to-routing

Verilog to Routing -- Open Source CAD Flow for FPGA Research

Language:C++License:NOASSERTIONStargazers:995Issues:0Issues:0

EvaluationFramework

Vivado scripts for the measuring the divide between academic and commercial FPGA CAD flows

Language:VHDLStargazers:3Issues:0Issues:0

OpenFPGA

An Open-source FPGA IP Generator

Language:VerilogLicense:MITStargazers:784Issues:0Issues:0

prjxray

Documenting the Xilinx 7-series bit-stream format.

Language:PythonLicense:ISCStargazers:1Issues:0Issues:0

RapidSmith2

RapidSmith2 - the Vivado successor to RapidSmith. Released Jan 4, 2017.

Language:JavaLicense:NOASSERTIONStargazers:41Issues:0Issues:0

tincr

A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite

Language:TclLicense:GPL-2.0Stargazers:39Issues:0Issues:0

prjxray

Documenting the Xilinx 7-series bit-stream format.

Language:PythonLicense:ISCStargazers:753Issues:0Issues:0

arachne-pnr

Place and route tool for FPGAs

Language:C++License:MITStargazers:414Issues:0Issues:0

hal

HAL – The Hardware Analyzer

Language:C++License:MITStargazers:534Issues:0Issues:0

debit

Reverse-engineering tools for FPGA bitstreams, Altera and Xilinx

Language:CLicense:GPL-3.0Stargazers:76Issues:0Issues:0

nextpnr

nextpnr portable FPGA place and route tool

Language:C++License:ISCStargazers:20Issues:0Issues:0

f4pga-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

Language:PythonLicense:Apache-2.0Stargazers:10Issues:0Issues:0

yosys

SymbiFlow WIP changes for Yosys Open SYnthesis Suite

Language:C++License:ISCStargazers:37Issues:0Issues:0

yosys-f4pga-plugins

Plugins for Yosys developed as part of the F4PGA project.

Language:VerilogLicense:Apache-2.0Stargazers:83Issues:0Issues:0

FPGA-Tool-Performance-Visualization-Library

FTPVL is a library for simplifying the data collection and visualization process for Symbiflow development.

Language:PythonLicense:MITStargazers:6Issues:0Issues:0

prjuray

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

Language:SystemVerilogLicense:Apache-2.0Stargazers:70Issues:0Issues:0

edalize

An abstraction library for interfacing EDA tools

Language:PythonLicense:BSD-2-ClauseStargazers:6Issues:0Issues:0

vtr-verilog-to-routing

SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research

Language:C++License:NOASSERTIONStargazers:37Issues:0Issues:0

prjtrellis

Documenting the Lattice ECP5 bit-stream format.

Language:PythonLicense:NOASSERTIONStargazers:50Issues:0Issues:0

icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)

Language:PythonLicense:ISCStargazers:32Issues:0Issues:0
Language:CStargazers:2Issues:0Issues:0

zynq-ultrascale-readback-capture

This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the same task to Zynq UltraScale+ MPSoC with several noticeable differences.

Language:TclStargazers:13Issues:0Issues:0

fos

FOS - FPGA Operating System

Language:VHDLLicense:NOASSERTIONStargazers:62Issues:0Issues:0
Language:CStargazers:21Issues:0Issues:0
Language:TclStargazers:14Issues:0Issues:0

yosys

Yosys Open SYnthesis Suite

Language:C++License:ISCStargazers:3329Issues:0Issues:0