chipsalliance / f4pga-examples

Example designs showing different ways to use F4PGA toolchains.

https://f4pga-examples.readthedocs.io

chipsalliance/f4pga-examples Issues

litex_demo top.bit not found
Updated 3 months ago
btn_counter on Arty a7?
Updated 5 months ago
linux_litex_demo VexRiscv_Linux.v needed by arty_35/top.eblif
Updated 5 months ago
litex produces non-functional bitfile for digilent cmod a7 35t with symbiflow
Updated 10 months ago8
Update README files of xc7/Example-Projects to add instructions for removing the generated files produced during the build process.
Updated a year ago
PicoSoC demo does not work out of the box
Updated a year ago3
Conda can't resolve packages for aarch64
Updated a year ago9
The final installation command is very easy to mess up
Closed a year ago2
Documentation: How to keep install instructions up to date?
Updated a year ago9
Built in gates cannot take multi-bit signal (Surelog)
Updated a year ago4
Localparam not working properly
Updated a year ago4
Update litex_demo to use F4PGA flow and current LiteX
Updated a year ago
add support for xc7a50tfgg484-1
Updated a year ago
What happened to the LiteX Linux and LiteX SATA demos?
Closed 2 years ago1
It is very hard to find the design / example list now
Updated 2 years ago6
Clock name or pattern 'pll.clk_in1' does not correspond to any nets.
Closed 2 years ago1
make: f4pga: No such file or directory make: *** [Makefile:10: build] Error 127
Updated 2 years ago3
JTAG init failed with: unable to open ftdi device
Closed 2 years ago2
Signal not in Net List with one bit wires
Closed 2 years ago3
SYMBIFLOW-CLASSROOM Surelog/UHDM and enum's
Closed 2 years ago3
Typedef Enum Width Default to one bit
Closed 2 years ago6
Array does not work with integers
Closed 2 years ago6
Unable to handle Shift with Ternary operator
Closed 2 years ago6
Codebreaker Lab Failure
Closed 2 years ago6
SYMBIFLOW-CLASSROOM Surelog/UHDM doesn't handle typed parameters
Closed 2 years ago5
SYMBIFLOW-CLASSROOM Surelog/UHDM Doesn't Handle `default_nettype none
Closed 2 years ago4
SYMBIFLOW-CLASSROOM Surelog/UHDM Don't Support Verilog Built-In Gates
Closed 2 years ago10
String Parameters not supported with Surelog-yosys Plugin
Closed 2 years ago4
Flow continues with Undefined Type Error using Surelog
Closed 2 years ago4
Switch to using openFPGALoader as the default tool to upload bitstreams to xc7 devices
Closed 2 years ago
Symbiflow-classroom: Array Initializers Do Not Work
Updated 2 years ago4
Convert examples to use `f4pga build` instead of makefiles
Updated 2 years ago7
Symbiflow-classroom: "Message: Failed to find matching architecture model for 'RAMB36E1'"
Closed 2 years ago24
Symbiflow-classroom: Surelog/UHDM and multi-bit input signals
Closed 2 years ago6
Symbiflow-classroom: Older style parameter declarations not supported
Closed 2 years ago6
Bump arch-defs packages and install f4pga through pip
Closed 2 years ago1
Document how to update/override specific tools
Updated 2 years ago
project-f.rst (and likely others): broken link
Closed 2 years ago1
Couldn't read file /scripts/xc7/synth.tcl
Closed 2 years ago10
Symbiflow-classroom: Parameterizing top-level module
Closed 2 years ago3
Symbiflow-classroom: MMCM placement error
Closed 2 years ago9
Symbiflow-classroom: "Error declaring a variable inside an always_comb block"
Updated 2 years ago4
Symbiflow-classroom: "Multiple include causes error"
Updated 2 years ago3
Symbiflow-classroom:Reset of BRAM Output Register
Updated 2 years ago11
Symbiflow-classroom: Initialization of memories using $readmemh()
Updated 2 years ago4
Question: Possible to test tools without .xdc file?
Updated 2 years ago4
Symbiflow_synth : "-- Parsing `counter.v' using frontend ` -vlog2k' -- ERROR: Can't open input file `counter.v' for reading: No such file or directory
Updated 2 years ago1
Yosys version not moving forward automatically? Need to make sure we are on HEAD
Updated 2 years ago5
Create a demo for the NiteFury / Acorn boards
Updated 2 years ago
Strip spaces from variables TOP and TARGET in common/common.mk
Closed 3 years ago2