YosysHQ / yosys

Yosys Open SYnthesis Suite

https://yosyshq.net/yosys/

YosysHQ/yosys Issues

Latch inferred for x signal
Updated 10 days ago1
Reduce default severity of Verific messages that produce warnings on commonly used coding styles
Updated 10 days ago
Yosys Fails to Detect Syntax Violations According to Verilog Standards
Updated 13 days ago2
Proof engine is going into wrong case in case statement
Closed 13 days ago3
Parameters in other packages
Updated 15 days ago2
Area and timing constraints for ASIC synthesis
Updated 15 days ago1
yosys fails with 'ERROR: init_share_dirname: unable to determine share/ directory!' on macos
Closed 16 days ago3
Hang on a loop when write_cxxrtl
Updated 17 days ago3
Assertion Failure in genrtlil.cc When Handling Signedness Issue Description:
Updated 18 days ago1
Extreme logic usage
Closed 25 days ago10
Yosys not removing DFF with constant input and replacing with a constant driver.
Closed 24 days ago10
Top package import error
Closed 25 days ago2
Cannot build yosys in Ubuntu following instructions in README
Closed 25 days ago13
opt_merge merges $assert cells
Updated 25 days ago1
ABC9/AIGER (synth_ecp5) crash "Executing AIGER Frontend" std::vector<_Tp, _Alloc>::.... Assertion '__n < this->size()' failed.
Updated a month ago6
Failed to Find a Submodule during Verilog Synthesis
Closed a month ago1
ERROR: Visited AIG node more than once; this could be a combinatorial loop that has not been broken
Updated a month ago2
Keep attribute not working as expected
Updated a month ago9
intel/common/brams_map_m9k.v widthad_* and width_* swapped
Updated a month ago2
synthesis bug as terminate called after throwing an instance of 'std::length_error'
Closed a month ago1
Bit-width type conversion causes array overflow
Closed a month ago1
latch inferred in synthesis process
Closed a month ago1
Performance regression in Yosys 0.39
Updated a month ago6
Use of system functions in localparam value prevents resolution of port
Updated a month ago1
Have a way to inject extra techmapping rules when calling `synth`
Closed a month ago
AST fails to handle implicit wires properly
Updated a month ago3
abc9 crash on synth_ice40 in Yosys 0.38
Updated a month ago10
`share` stuck on a combinational loop
Updated a month ago
Proposals for new selection syntax specifiers
Updated a month ago
Add NetBSD support
Updated a month ago2
Synthesis fails with the latest yosys.
Closed 2 months ago2
`begin_keywords directive
Updated 2 months ago
Please add a flag to generate a simplified graphviz diagram.
Updated 2 months ago14
Incorrect BitVector width in SMT2 code produced by yosys
Closed 2 months ago4
CXXRTL: assert '!for_debug' failed with `write_cxxrtl -g4`
Closed 2 months ago7
[Show command] Preserve the order of module inputs and outputs in the generated diagram.
Updated 2 months ago
Verilog asynchronous reset pattern leads to corrupted `$check`, `$print` control signals
Updated 2 months ago8
CXXRTL: blackbox output ports cannot generate clock events
Updated 2 months ago2
cxxrtl hangs on a loop
Updated 2 months ago3
Verific doesn't represent write port priority
Updated 2 months ago
It seems that a compilation syntax error occurred with yosys
Updated 2 months ago2
Support for GAL and ATF-series SPLDs
Updated 2 months ago1
Registers created by "write_smt2" could be wires by"write_verilog"
Updated 2 months ago
Discrepancy what happens on `read -vlog2k; hierarchy;` depending on Verific presence
Closed 2 months ago3
`memory_collect` makes up priority relationships between two `$memwr`
Updated 2 months ago
Add an option to synth to enable the booth lower power option
Updated 2 months ago7
synth docs miss booth in the steps
Closed 2 months ago
BUG：Issue in Yosys Synthesis: 'std::length_error' Leads to Termination
Closed 3 months ago11
ABC9 on ice40 causing "ERROR: Visited AIG node more than once; this could be a combinatorial loop that has not been broken"
Updated 3 months ago1
Misoptimization of wide shifts
Updated 3 months ago3