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arachne-pnr

Place and route tool for FPGAs

bitman

Datamining

debit

Reverse-engineering tools for FPGA bitstreams, Altera and Xilinx

edalize

An abstraction library for interfacing EDA tools

efcad

EvaluationFramework

Vivado scripts for the measuring the divide between academic and commercial FPGA CAD flows

fos

FOS - FPGA Operating System

FPGA-Tool-Performance-Visualization-Library

FTPVL is a library for simplifying the data collection and visualization process for Symbiflow development.

fpgatools

public domain tools for FPGAs

hal

HAL – The Hardware Analyzer

hello-world

icestorm

Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)

nextpnr

nextpnr portable FPGA place and route tool

OpenFPGA

An Open-source FPGA IP Generator

prjtrellis

Documenting the Lattice ECP5 bit-stream format.

prjuray

Documenting the Xilinx Ultrascale, Ultrascale+ and UltraScale MPSoC series bit-stream format.

prjxray

Documenting the Xilinx 7-series bit-stream format.

python-symbiflow-v2x

Tool for converting specialized annotated Verilog models into XML needed for Verilog to Routing flow.

RapidSmith2

RapidSmith2 - the Vivado successor to RapidSmith. Released Jan 4, 2017.

SymbiYosys

SymbiYosys (sby) -- Front-end for Yosys-based formal verification flows

tincr

A Tcl-based CAD Tool Framework for Xilinx's Vivado Design Suite

vtr-verilog-to-routing

SymbiFlow WIP changes for Verilog to Routing -- Open Source CAD Flow for FPGA Research

yosys

Yosys Open SYnthesis Suite

yosys-symbiflow-plugins

Plugins for Yosys developed as part of the SymbiFlow project.

zynq-ultrascale-readback-capture

This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the same task to Zynq UltraScale+ MPSoC with several noticeable differences.

zynq_driver