Xiongfei(Alex) GUO (xfguo)

xfguo

Geek Repo

Company:Jinglue Semi. (SH) Inc.

Location:Shanghai, China

Home Page:http://www.linkedin.com/in/xfguo

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Organizations
jlsemi
riscv

Xiongfei(Alex) GUO's starred repositories

yosys

Yosys Open SYnthesis Suite

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OpenFPGA

An Open-source FPGA IP Generator

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wavedrompy

WaveDrom compatible python command line

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asciidoctor.js

:scroll: A JavaScript port of Asciidoctor, a modern implementation of AsciiDoc

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AsciiDocBox

Live AsciiDoc Editor.

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scratchip

scratchip is a framework that can help to build your Chisel and Verilog/Systemverilog project easier.

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netlistsvg

draws an SVG schematic from a JSON netlist

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webfsd

A simple HTTP server for mostly static content written in C

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docker-ubuntu-vnc-desktop

A Docker image to provide web VNC interface to access Ubuntu LXDE/LxQT desktop environment.

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ngspice

mirror of ngspice repo at git://git.code.sf.net/p/ngspice/ngspice ngspice-ngspice

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netgen

Netgen complete LVS tool for comparing SPICE or verilog netlists

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bsg_fakeram

fakeram generator for use by researchers who do not have access to commercial ram generators

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nextpnr

nextpnr portable FPGA place and route tool

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fpga-rocket-chip

Wrapper for Rocket-Chip on FPGAs

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klayout

KLayout Main Sources

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TritonRoute

UCSD Detailed Router

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wujian100_open

IC design and development should be faster,simpler and more reliable

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skywater-pdk

Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.

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chisel3-releases

Unofficial Releases Package All Dependencies of Chisel3 and FIRRTL

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OpenROAD

OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

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armv7-nexus7-grsec

Hardened PoC: PaX for Android

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swerv_eh1

A directory of Western Digital’s RISC-V SweRV Cores

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breadbee

Breadboard-able Cortex A7 dev board

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cdpga

FPGA core boards / evaluation boards based on CDCTL hardware

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diplomacy

split from rocketchip, try to add test and doc to it.

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phytool

Linux MDIO register access

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chisel-ipxact

Generating IP blocks fit for simulation from SystemC from Chisel from Template-Chisel from XML.

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chisel-packaging

IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.

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