You may only want to use rocket-chip as a series of libraries. This project will be a good start.
Clone and upate submodules.
git clone https://github.com/xfguo/chisel-template-w-rocket-chip.git
cd chisel-template-w-rocket-chip
git submodule update --init
cd lib/rocket-chip
git submodule update --init
Build from chisel to verilog.
cd ../../
make verilog
You can find out generated .fir
and .v
files at ./builds
.
Contributors
- Alex Guo xfguo@xfguo.com
- Colin Lin colin4124@gmail.com