wataru030-XIAOHEI

rocket-chip

Rocket Chip Generator

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

pygears

HW Design: A Functional Approach

KyogenRV

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

My-RISCV64-CORE-writing

一生一芯 ， ysyx ， npc . the repo of the YSYX project . a riscv-64 CPU . writing .

SOL-s-Verilog-Cheatsheet-for-Not-So-Beginners

All-of-SystemVerilog

みんなのSystemVerilog

ritter-soc

a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog

Nova132

A classic five stage pipelined processor

homemade-riscv

『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ

Nova132A

基于Nova132优化的七级流水线处理器

pygears_riscv

RISC-V processor implementation in PyGears

All-of-SystemVerilog

みんなのSystemVerilog

FPGAdasai

the files of the fpga games

FPGAStudyNotebook