Wataru030's repositories
My-RISCV64-CORE-writing
一生一芯 , ysyx , npc . the repo of the YSYX project . a riscv-64 CPU . writing .
study_notebook
my study notebook.我的学习记录,包括chisel笔记,计算机体系结果等。
xilinx_tcp_adc_data_recv
一个PLadc数据采集,PS以太网lwip接收数据到PC的vivado工程。
All-of-SystemVerilog
みんなのSystemVerilog
RV64-ISA-book
是RV64各指令的解释,简体中文。RV64's inst description . Simple chinese.
computer-systems-ucas
**科学院大学 计算机组成原理FPGA实验课程 - "Five projects to better understand key principles of computer systems", UCAS Spring 2017 Session
homemade-riscv
『プログラマのためのFPGAによるRISC-Vマイコンの作り方』のサポート・リポジトリ
KyogenRV
The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
NutShell
RISC-V SoC designed by students in UCAS
pygears
HW Design: A Functional Approach
riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
ritter-soc
a 4-pipeline riscv soc , based with rv32im ,designed by verilog
rocket-chip
Rocket Chip Generator