tum-ei-eda / M2-ISA-R

CoreDSL2 Parser with backend to generate simulation code for the ETISS instruction set simulator

https://tum-ei-eda.github.io/M2-ISA-R/

tum-ei-eda/M2-ISA-R Issues

Sliced width is ignored during concatenation
Updated a year ago2
Type casting
Updated a year ago1
Left-hand indexing not supported
Updated a year ago1
Generate ETISS VirtualStruct for all registers
Updated a year ago1
Memory access code generation needs an overhaul
Closed a year ago1
PC access in functions does not yield correct results
Updated 2 years ago4
Access of [[is_main_mem]] Memories does not work within functions
Closed 2 years ago
Memory read inside if-statement not generating correct code
Closed 2 years ago2
return statement does not translate PC access correctly
Updated 2 years ago
slicing is not working correctly for extern variables
Closed 2 years ago3
Overflow dropping in summation operation
Updated 2 years ago2
Wrong code is generated in concatenation operation
Closed 2 years ago2
Nested static statements
Closed 3 years ago7
GDB Register Print Support in `RISCVVGDBCore.h`
Closed 3 years ago1
Index to Register File for Compressed Instructions not correctly handled
Updated 3 years ago4
Include some examples / automated testing with github actions
Closed 3 years ago1