EDA@TUM (tum-ei-eda)

EDA@TUM

tum-ei-eda

Geek Repo

Open Source Repository of the ESL Group of the Chair of Electronic Design Automation, TU Munich

Location:Munich, Germany

Home Page:https://www.ce.cit.tum.de/en/eda/research/electronic-system-level/

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EDA@TUM's repositories

muriscv-nn

muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.

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etiss

Extendable Translating Instruction Set Simulator

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mlonmcu

Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends

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vrtlmod

vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/Clang-Tools and generates a fault injection API.

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seal5

Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization

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M2-ISA-R

CoreDSL2 Parser with backend to generate simulation code for the ETISS instruction set simulator

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etiss-sc

SystemC/TLM2.0 productivity library wrapping the Extendable Instruction Set Simulator ETISS as a tlm cpu core.

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softvector

Vector arithmetic library targeting simulation of Vector Processing Units (VPUs) for various targets, e.g., ETISS.

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Trace-Generator

Python tool to generate monitors (and printers) for ETISS based on json description

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micro-kws

Complete flow for keyword spotting on microcontrollers. From data collection to data preparation to training and deployment.

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mlonmcu-models

TinyML model zoo primarily used by the MLonMCU python package

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mlonmcu-sw

Target software library (MLIF, Machine Learning Interface) used by the MLonMCU python package

RISCV_ISA_CoreDSL

CoreDSL descriptions of the RISC-V ISA

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tvm

Open deep learning compiler stack for cpu, gpu and specialized accelerators

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CoreV_ISA_CoreDSL

CoreDSL descriptions of the Core-V ISA Extension (https://cv32e40p.readthedocs.io/en/latest/instruction_set_extensions.html)

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etiss-perf-sim

ETISS-based performance simulator

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etiss_arch_riscv

RISC-V architecture models for ETISS

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PerformanceSimulation_workspace

Example workspace for software performance simulation with ETISS-based performance simulator

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seminar_generator

Excel generator for the student seminars (GradingSheets, Agenda, GradingReport)

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tflite-pack

Packing Utils for TFLite Models

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