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tum-ei-eda / M2-ISA-R

CoreDSL2 Parser with backend to generate simulation code for the ETISS instruction set simulator

Home Page:https://tum-ei-eda.github.io/M2-ISA-R/

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Generate ETISS VirtualStruct for all registers

wysiwyng opened this issue · comments

commented

Requested from ETISS: tum-ei-eda/etiss#122

Open questions:

  • Should register banks be generated as X[0]... ?
  • Should aliased registers keep their alias name?
commented

This is currently in concept phase