rejunity / Atari-2600-FPGA

Continue development of Atari 2600 in Verilog. Based on the original work by Daniel Beer.

Atari-2600

Atari 2600 in Verilog.

Based on the Daniel Beer's earlier work "Atari on an FPGA".

Plan

1. Replace CPU 6502 VHDL implementation with Verilog.
   • Integrate Andrew Holme Verilog 6502 core
   • Integrate Arlet Ottens Verilog 6502 core

• Minimize vendor dependent code, move it out of the main files.
  • Remove PLL from mySystem.v
  • Separate folder for IceBreaker and Altera specific code
• Make codebase compatible with the open-source tools: iverilog, yosys.
  • Makefile
• Testbench, coco_tb, compare to python emu
• Try to fit on open-source iCEBreaker FPGA (Lattice iCE40UP5k).
• ASIC! :)