parkjjoe / stopwatch

Design a Stopwatch with Verilog HDL

digital fsm segment stopwatch verilog verilog-hdl vhdl

Stopwatch

Design a stopwatch with Verilog HDL

Stopwatch FSM

When the Start button is pressed, the stopwatch starts or pauses. Pressing the Soft Reset button resets the display to 00.00.00. Pressing the Hard Reset button first displays 0 on the rightmost segment and then resets the display to 00.00.00.

Stopwatch Block Diagram

Segment Display Controller FSM

seg_controller FSM

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Design a Stopwatch with Verilog HDL

digital fsm segment stopwatch verilog verilog-hdl vhdl

MIT License

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Language:Verilog 100.0%