mattvenn

matt venn's repositories

wokwi-verilog-gds-test

Language:VerilogApache-2.055 3 7

flipflop_demo

Flip flop setup, hold & metastability explorer tool

Language:Jupyter NotebookApache-2.029 5 1

zero_to_asic_mpw7

Language:VerilogApache-2.05 30

gf180-demo

Language:VerilogApache-2.0100

tinytapeout-7seg-seconds-counter

Language:VerilogApache-2.01 20

tomverbeure.github.io

100

wokwi_filler

Language:VerilogApache-2.0100

caravel_user_project-1

Language:VerilogApache-2.0000

clockless-inverter

Language:Tcl000

nibblecpu

Proof of Concept to learn Amaranth as an entry effort for Supercon's RTL design competition

Language:PythonBSD-2-Clause000

tinytapeout-341802448429515346

Language:VerilogApache-2.0000

tinytapeout-341802655228625490

Language:VerilogApache-2.0000

tinytapeout-7seg-decoder

Language:VerilogApache-2.0000

tinytapeout-all-one

Language:VerilogApache-2.0000

tinytapeout-all-zero

Language:VerilogApache-2.0000

tinytapeout-demo1

Language:VerilogApache-2.0000

tinytapeout-laura

Language:VerilogApache-2.0020

tinytapeout-marc

Language:VerilogApache-2.0000

tinytapeout-test-invert

Language:VerilogApache-2.0000

tinytapeout-test-straight

Language:VerilogApache-2.0000

tinytapeout-verilog-test

Language:VerilogApache-2.0000

tinytapeout_m_segments

Language:VerilogApache-2.0000

tinytapeout_scan

Language:Verilog000

tinytapeout_spin0

Basic spin animation on LED 7 segment

Apache-2.0000

tristate

Language:Verilog000

tt001

Language:VerilogApache-2.0000

tt_000

000

wokwi_inverters

Language:VerilogApache-2.0000

wrapped_ibnalhaytham

RISC-V based 32-bit pipelined processor + memory controler

Apache-2.0000

wrapped_snn_network

Language:VerilogApache-2.0000