Verilog IO Linker
- Enginner: Kermit
- Company: LiscoTech
- Version: 1.0.0
- Date: 20200330
- Python: 3.5.5
Note
- Auto generate verilog IO instance
- Replace IO bitwidth parameters
- Left comma mode switch
- Load module from file
- Support GUI: wxpython
- WIP
- Generate code autoly go in clipboard
Version Log
1.0.0
- New architecture
- Module manager
- Load file
- Create parameter
- Create IO/wire
- Generate file function
- New IO/wire link function
0.2.1
- FixBug
- Parameter with under line mode
0.2.0
- Add
- Parameter mapping mode (name or value)
- Wire under line mode
- FixBug
- Parse the comment function
0.1.0
- Add
- Assign output/input switch
- GUI check box for assign
- GUI auto generate instance name
0.0.0
- Basic function