kermit0124

pyui4win

一个用python实现业务逻辑、用xml和html/css/js描述界面的windows程序的快速开发框架。该框架将duilib运行时和python运行时结合到一起，实现用xml快速构建界面的同时，利用python及其众多久经考验的库编写业务逻辑，极大地缩短开发周期。

_ftdi

FTDI232RL bitbang and FTDI232H I2C/SPI experimentations

awesome-selfhosted

A list of Free Software network services and web applications which can be hosted on your own servers

biriscv

32-bit Superscalar RISC-V CPU

bsp-xilinx

cmd_vivado

Simplified Command Line Interface to Xilinx's Vivado IDE

cocotb-example

code_helper

Cores-SweRV-EL2

SweRV EL2 Core

Cores-SweRVolf

FuseSoC-based SoC for SweRV EH1

crawler_rent_591

DearPyGui

Dear PyGui: A fast and powerful Graphical User Interface Toolkit for Python with minimal dependencies

FPGA-ftdi245fifo

FPGA-based USB fast communication using FT232H/FT600 chip.

imgui

Dear ImGui: Bloat-free Graphical User interface for C++ with minimal dependencies

litex

Build your hardware, easily!

neorv32

🖥️ A tiny, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.

nicegui

High-Level Abstraction Web-GUI Using Just Python.

notence

📝 An open source personal note-taking app inspired by notion.so (Alpha📌)

pointer_queue

C99 queue base on pointer buffer

printf

Tiny, fast, non-dependent and fully loaded printf implementation for embedded systems. Extensive test suite passing.

proto245

🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)

ruckus

Vivado build system

serv

SERV - The SErial RISC-V CPU

tinyriscv

A very simple and easy to understand RISC-V core.

toga

A Python native, OS native GUI toolkit.

tree-sitter

An incremental parsing system for programming tools

usb_sniffer

High Speed USB 2.0 capture device based on miniSpartan6+

USBCore

USB Full-Speed/Hi-Speed Device Controller core for FPGA

verible

Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, and formatter.

verilog_IO_linker

A gadget for verilog module link