kermit0124

AMBA

Collection of IPs based on AMBA (AHB, APB, AXI) protocols

arty_xjtag

Xilinx JTAG Toolchain on Digilent Arty board

axi_node

AXI X-Bar

core_usb_bridge

USB -> AXI Debug Bridge

cores

Various HDL (Verilog) IP Cores

daisho

Test of the USB3 IP Core from Daisho on a Xilinx device

darkriscv

opensouce RISC-V implemented from scratch in one night!

fpga-spi

Simple SPI interface for FPGAs

gen_amba

AMBA bus generator including AXI, AHB, and APB

hwt

VHDL/Verilog/SystemC code generator, simulator writen in python/c++

mriscvcore

A 32-bit RISC-V processor for mriscv project

MyMDwiki

Mdwiki

pars

pyboostnote

boostnote.io python data handler(impoter / expoter)

pyftdi

FTDI device driver written in pure Python

python-cheatsheet

Comprehensive Python Cheatsheet

python-is-cool

Cool Python features for machine learning that I used to be too afraid to use

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

SuperScalar-RISCV-CPU

super-scalar out-of-order RV32IMC cpu core,4 DMIPS/MHz(best), 2 DMIPS/MHz(legal)

uiscontrol

Control the UIS-522b via send package

verilog-axi

Verilog AXI components for FPGA implementation

verilog-axis

Verilog AXI stream components for FPGA implementation

verilog-i2c

Verilog I2C interface for FPGA implementation

verilog-uart

Verilog UART

xfcp

Extensible FPGA control platform