This package provides a mechanism for interacting with the Xilinx Vivado IDE through a simplified command line tool. Vivado provides a Tcl based interface to programatically avoid the GUI, but it is too low level to directly interact with a build system. This package provides an interface suitable to be used with build tools such as Make.
cmd_vivado
works by running the Vivado IDE in Tcl mode as a server
(vivado_server.py
). This is advantageous as Vivado takes several (~8 on my
current machine) seconds to start up. The client (vivado_client.py
) provides
a simplified command line interface to the synthesize, place, route, and program
workflow. The client communicates to the server through sockets. Theoretically
the server could run remotely from the client, although this has not been
tested.
./vivado_server.py --exec_path=~/VivadoPath/bin/vivado
./vivado_client.py command --options
The client currently implements the following commands:
synth
- Synthesize a design.place
- Place a synthesized design.route
- Route a placed design.bitstream
- Write a.bit
bitstream.cfg_mem
- Write a.bin
configuration memory file.load
- Load a bitstream onto a device.flash
- Flash a configuration onto on-board flash.
Further information can be sought with the --help
option.
make all
The provided Makefile
shows how to combine cmd_vivado
with a build tool for
a rudimentary workflow. Verbosity can be increased with make VERBOSE=1
.
The example
directory contains the simplest possible project that demonstrates
cmd_vivado
use with a Makefile
. It is targeted at the Digilent Arty A7
A35T
development board.
- Install Vivado including drivers (requires an extra step on Linux).
- Plug in the Arty A7 micro USB.
- Start the server with
./vivado_server.py exec_path=VIVADO_PATH
. Make sure to changeVIVADO_PATH
with path to your Vivado installation. - From the
example
directory runmake VERBOSE=1 flash
. - Wait for Vivado to do it's thing.
- Play with the buttons (
BTN[3:0]
) and observe LEDS (LED[7:4]
).
Currently cmd_vivado
has only the features required for the simplest
demonstration. I expect many features will need to be added for it to be useful
in non-trivial projects, but hopefully this framework will provide a good
starting point. I am learning about FPGAs as I go, and I welcome suggestions.
- Explore ways to speed up various parts of workflow.
- Explore Out Of Context (OOC) workflow and how it could be leveraged for incremental compilation.