kele14x

Microsoft-Activation-Scripts

A Windows and Office activator using HWID / Ohook / KMS38 / Online KMS activation methods, with a focus on open-source code and fewer antivirus detections.

ollama

Get up and running with Llama 3.1, Mistral, Gemma 2, and other large language models.

drawio-desktop

Official electron build of draw.io

bulma

Modern CSS framework based on Flexbox

ComfyUI

The most powerful and modular diffusion model GUI, api and backend with a graph/nodes interface.

ZeroTierOne

A Smart Ethernet Switch for Earth

mosh

Mobile Shell

yolov9

Implementation of paper - YOLOv9: Learning What You Want to Learn Using Programmable Gradient Information

mini-rv32ima

A tiny C header-only risc-v emulator.

inja

A Template Engine for Modern C++

rsd

RSD: RISC-V Out-of-Order Superscalar Processor

WinSetView

Globally Set Explorer Folder Views

scr1

SCR1 is a high-quality open-source RISC-V MCU core in Verilog

sionna

Sionna: An Open-Source Library for Next-Generation Physical Layer Research

riscv-sodor

educational microarchitectures for risc-v isa

riscv-opcodes

RISC-V Opcodes

rv

32-bit RISC-V CPU in ~800 lines of C89

riscv-pk

RISC-V Proxy Kernel

dma_ip_drivers

Xilinx QDMA IP Drivers

riscv-mini

Simple RISC-V 3-stage Pipeline in Chisel

mor1kx

mor1kx - an OpenRISC 1000 processor IP core

m.css

A no-nonsense, no-JavaScript CSS framework, site and documentation theme for content-oriented websites

rvemu-for-book

Reference implementation for the book "Writing a RISC-V Emulator in Rust".

xdna-driver

RV12

RISC-V CPU Core

hexo-theme-murasaki

Yet another minimalist theme for Hexo. (EARLY DEV STAGE)

morty

A SystemVerilog source file pickler.

list_of_Xilinx_FPGAs

VD100_2023.2

The VD100 development board is based on the Xilinx Versal AI Edge series chip xcve2302 and is designed with a core board and a bottom board.

ZCU670_Ethernet_TRD

ZCU670 IEEE 1588 Ethernet TRD