johan92

fpga-hash-table

Simple hash table on Verilog (SystemVerilog)

verilog-coding-style

Verilog (SystemVerilog) coding style

yafpgatetris

Yet Another Tetris on FPGA Implementation

csr-map-generator

Generator for CSR mapping module

altera_opencl_sandbox

fpga-risc-16

Making RISC-16 for academic purposes

fpga-shared-memory

Verilog (SystemVerilog) implementation of shared memory for multiport systems

fpga-sort-engine

Simple sort engine on Verilog.

Bloom_pattern_search

Pattern search based on Bloom algorithm.

fpga-for-beginners

Repo with FPGA/Verilog/RTL examples. I use it in articles for demonstration.

fpga-multiflow-pkt-gen

Try to implement multiflow packet generator with various rate settings

fpga-quadtree

johan92.github.io

My blog on github :)

s5_a10_ram_test

Simple project for M20K read/writing. It shows some problems in timing in Arria 10.