Giters
jeanthom
/
gram
DDR3 controller for nMigen (WIP)
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Stargazers:
13
Watchers:
5
Issues:
54
Forks:
1
jeanthom/gram Issues
Bring back testing in gram
Updated
4 years ago
Comments count
5
PyPI package name conflict
Updated
4 years ago
Comments count
1
Change primitive for Address/Command output
Updated
4 years ago
Comments count
1
Reliability issues when doing memtests
Updated
4 years ago
Comments count
14
Move DQS related code into a DQSGroup elaboratable
Updated
4 years ago
Comments count
1
Multiplexer bug is not detected by test suite
Updated
4 years ago
Wishbone ack doesn't take rddata_valid into account
Closed
4 years ago
Comments count
2
DQSBUFM's pause/readclksel sequence is wrong
Closed
4 years ago
Timing violations reported by FakePHY
Closed
4 years ago
Comments count
5
Replace asserts with proper exceptions
Closed
4 years ago
Sync data readout to DQSBUFM's datavalid
Closed
4 years ago
Use dramsync as the default clock domain everywhere in gram
Closed
4 years ago
Publish gram on PyPI
Updated
4 years ago
Default to SEL=1 if SEL=0
Closed
4 years ago
sel signal is buggy
Closed
4 years ago
AXI frontend
Updated
4 years ago
Add cti and bte to Wishbone frontend
Updated
4 years ago
Avoid usage of getattr
Closed
4 years ago
Comments count
1
Add ECP5 builds to SourceHut builds
Updated
4 years ago
Comments count
1
Use upstream platform file
Closed
4 years ago
Comments count
1
Burst detection is not working
Closed
4 years ago
Comments count
2
Generate MRx values according to DRAM chip specs
Updated
4 years ago
Comments count
1
Read issues after a write transaction
Closed
4 years ago
Comments count
1
Add more assertions to the CRG simulation
Closed
4 years ago
Comments count
1
Customizable data width on wishbone frontend
Closed
4 years ago
Comments count
1
Externalize RoundRobin
Closed
4 years ago
Comments count
2
Include CRG in gram
Closed
4 years ago
Fix bank activation failure
Closed
4 years ago
Comments count
2
max_time is never set to 1 when time counter is null (in Icarus Simulation)
Closed
4 years ago
Comments count
3
Memtest fail
Closed
4 years ago
Comments count
12
Write transactions aren't properly detected by the DRAM model
Closed
4 years ago
Comments count
2
Parallelize unit tests
Closed
4 years ago
Comments count
1
Fix tDLLK violation
Closed
4 years ago
Comments count
1
Use PinsN for RAS/CAS/WE
Closed
4 years ago
Comments count
3
Use Up-Down converters from nmigen-soc
Closed
4 years ago
Critical path too long in dram core
Closed
4 years ago
Comments count
5
ECP5 CRG is wonky
Closed
4 years ago
Report software version in CI
Closed
4 years ago
Comments count
3
DRAM is not responding to read requests
Closed
4 years ago
Comments count
2
Add SymbiYosys to SourceHut builds
Closed
4 years ago
Comments count
2
Long critical path between refresher and somewhere in controller
Closed
4 years ago
Comments count
1
PHY unit testing
Closed
4 years ago
Comments count
1
ECP5 PHY signal lignes are invalid
Closed
4 years ago
Comments count
2
Don't instantiate arbiters if there is only one master in crossbar
Closed
4 years ago
Comments count
1
"a" signal in RefreshExecuter and RefreshSequencer is too small
Closed
4 years ago
DQS group mismatch
Closed
4 years ago
Comments count
5
DQSBUFM not connected to top level
Closed
4 years ago
Comments count
1
ECP5DDRPHY is filled with "Case" statements but nMigen doesn't see anything wrong with it
Closed
4 years ago
Wishbone DRAM content interface debugging
Closed
4 years ago
Comments count
2
Multi-driven signals in DFII
Closed
4 years ago
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