hyperpicc

hyperpicc

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picorv32

PicoRV32 - A Size-Optimized RISC-V CPU

Language:VerilogLicense:ISCStargazers:2916Issues:164Issues:174

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Language:VerilogLicense:Apache-2.0Stargazers:2562Issues:229Issues:43

cva6

The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

Language:AssemblyLicense:NOASSERTIONStargazers:2153Issues:91Issues:979

cocotb

cocotb, a coroutine based cosimulation library for writing VHDL and Verilog testbenches in Python

Language:PythonLicense:BSD-3-ClauseStargazers:1693Issues:105Issues:1812

miaow

An open source GPU based off of the AMD Southern Islands ISA.

Language:VerilogLicense:BSD-3-ClauseStargazers:1002Issues:144Issues:16

cv32e40p

CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

Language:SystemVerilogLicense:NOASSERTIONStargazers:904Issues:83Issues:475

gplgpu

GPL v3 2D/3D graphics engine in verilog

Language:VHDLLicense:GPL-3.0Stargazers:647Issues:85Issues:8

aes

Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementation supports 128 and 256 bit keys.

Language:VerilogLicense:BSD-2-ClauseStargazers:319Issues:27Issues:9

ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Language:VerilogLicense:NOASSERTIONStargazers:305Issues:34Issues:4

sha256

Hardware implementation of the SHA-256 cryptographic hash function

Language:VerilogLicense:BSD-2-ClauseStargazers:304Issues:27Issues:13

RV12

RISC-V CPU Core

Language:SystemVerilogLicense:NOASSERTIONStargazers:275Issues:20Issues:15

gifenc

small C GIF encoder

swerv-ISS

Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator

R8051

8051 soft CPU core. 700-lines statements for 111 instructions . Fully synthesizable Verilog-2001 core.

Language:VerilogLicense:Apache-2.0Stargazers:157Issues:8Issues:3

ahb3lite_interconnect

AHB3-Lite Interconnect

Language:SystemVerilogLicense:NOASSERTIONStargazers:80Issues:9Issues:4

trng

True Random Number Generator core implemented in Verilog.

Language:VerilogLicense:BSD-2-ClauseStargazers:71Issues:6Issues:2

ahb3lite_apb_bridge

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

Language:SystemVerilogLicense:NOASSERTIONStargazers:39Issues:5Issues:3

plic

Platform Level Interrupt Controller

Language:SystemVerilogLicense:NOASSERTIONStargazers:34Issues:6Issues:8

sha512

Verilog implementation of the SHA-512 hash function.

Language:VerilogLicense:BSD-2-ClauseStargazers:33Issues:8Issues:2

Modular-Exponentiation

Verilog Implementation of modular exponentiation using Montgomery multiplication

light52

Yet another free 8051 FPGA core

Language:VHDLStargazers:28Issues:0Issues:0

VerilogCodeECC

Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field

Language:Jupyter NotebookStargazers:20Issues:3Issues:0

ahb3lite_memory

Multi-Technology RAM with AHB3Lite interface

Language:SystemVerilogLicense:NOASSERTIONStargazers:19Issues:5Issues:2

sockit_owm

SocKit 1-wire (onewire) master

Language:CLicense:NOASSERTIONStargazers:18Issues:6Issues:1

adv_dbg_if

Universal Advanced JTAG Debug Interface

Language:SystemVerilogStargazers:16Issues:5Issues:1

universal_jtag_tap

Universal JTAG TAP Controller

Language:SystemVerilogStargazers:9Issues:5Issues:0

sockit_spi

SocKit SPI (3-wire, dual, quad) master

Language:VerilogStargazers:5Issues:3Issues:0

light52

Lightweight 8051 compatible CPU

Language:VHDLStargazers:4Issues:3Issues:0

Embedded-8051-based-Cryptosystem

An embedded 8051-based crypto system with a cryptographic coprocessor

Language:VHDLStargazers:3Issues:4Issues:0